1. Field of the Invention
The present invention relates to phase locking two frequency sources together with offset frequencies, with the offset being substantially less than a tracking loop frequency response.
2. Description of the Related Art
Two frequency sources can be phase locked with a slight frequency offset using several conventional methods. If the desired offset is in the 1 Hz to 10 KHz range while the frequency sources operate near 10 GHz, undesirable design tradeoffs may result as detailed below.
A first circuit for phase locking two frequencies F1 and F2 with a small offset is illustrated in FIG. 1. The circuit includes two frequency synthesizers 102 and 104 phase locked to the same reference oscillator 100. Each synthesizer essentially is a phase locked loop (PLL). The synthesizers 102 and 104 include a phase detector having a first input connected to the reference oscillator 100 and a second input provided from a voltage controlled oscillator (VCO) providing the synthesizer output. The VCO has its output downconverted by a ÷N frequency divider to the frequency of the reference oscillator 100. The output of the phase detector provides a voltage indicating any phase difference between its inputs to control the VCO so that its frequency is phase locked with the oscillator 100. To provide the two synthesizers operating in the range as high as 10 GHz while still faithfully tracking the reference oscillator with an offset of 1 Hz to 10 KHz requires instrument grade synthesizers which are large and expensive. Such instrument grade synthesizers may be undesirable.
A second method of phase locking two frequency sources with a slight frequency offset is illustrated in FIG. 2. The circuit in FIG. 2 includes a first oscillator 200 set with an output frequency F1 and a second oscillator 202 with an output frequency F2 slightly offset from F1. The output of the oscillators 200 and 202 are mixed in mixer 204 to provide signals at frequencies F2xe2x88x92F1 and F2+F1. The output from mixer 204 is provided through a filter 206 to eliminate the F2+F1 component and pass the desired offset Fs=F2xe2x88x92F1. The output of the filter 206 is applied to a first input of a digital frequency/phase detector 208. A second input of the phase detector 208 is provided from an offset reference oscillator 210 operating at the desired offset frequency Fs=F2xe2x88x92F1. The phase detector 210 then provides an output indicating the phase/frequency difference between its inputs to a loop amplifier 212 which drives the tracking oscillator 202.
The loop bandwidth is typically constrained to 1/10 the offset Fs due to phase detector sampling limitations. The digital phase detector 208 typically operates using a sampling process that is updated on the rising or falling edge of the phase detector inputs. The sampling process has the same effect as a sample and hold circuit, where information is updated at a sampling frequency Fs. For a 1 Hz offset, the information into the loop amplifier 212 is updated every second. With a phase lag of 360xc2x0 between the signals provided to the phase detector 208, a pole is thus generated in the signal path with a 3 dB corner frequency at approximately 0.125 Hz with a phase shift of 45xc2x0.
A third approach would be to use a circuit with a linear phase detector, such as the four quadrant multiplier 300 shown in FIG. 3. The four quadrant multiplier 300 offers an advantage over a digital phase detector because it instantaneously responds to phase changes, so loop bandwidth will not be constrained to 1/10 Fs. A first input to the four quadrant multiplier 300 is provided from mixer 204 which mixes signals at frequencies F1 and F2 from signal sources 200 and 202 to provide a signal F2xe2x88x92F1 to the first input of the multiplier 300. A second input to the four quadrant multiplier 300 is provided from offset oscillator 210 which provides a signal at the desired offset frequency Fs=F2xe2x88x92F1. The four quadrant multiplier 300 then multiplies the analog signals provided to its inputs to provide a product signal 2Fs along with a DC signal indicating the phase difference xcfx86 between the inputs. The 2Fs signal can be filtered out using the filter 302 so that only the phase difference signal xcfx86 is provided to control the tracking oscillator 202.
Although filtering with filter 302 can remove the high frequency sum component 2Fs, with the offset being 1 Hz the filter 302 must be a 2 Hz device. The phase shift of the filter 302 will be at least 45xc2x0 times the number of poles generated at the 3 dB point. To reject the 2 Hz signal, a filter 212 would need to be at least 1.5 Hz with 5 to 6 poles at the 3 dB point of approximately 0.125 Hz. This would leave a designer no choice but to limit the loop bandwidth within 1/10 Fs to minimize phase shift within the control loop.
In accordance with the present invention, a linear phase detector is provided that cancels the 2Fs term while retaining the instantaneous bandwidth DC phase difference determination associated with a linear phase detector. In effect, an image reject mixer is provided with a DC phase difference component enhanced, and any 2Fs frequency component cancelled.
In accordance with the present invention, referring to FIG. 4, a linear phase detector is provided including an oscillator 400 and a VCO 402 operating with a slight frequency offset (F2xe2x88x92F1) or (F1xe2x88x92F2) from the oscillator 400, along with additional circuitry for phase locking the offset between the oscillator 400 and VCO 402 with another oscillator 404 operating at the desired offset (F2xe2x88x92F1 or (F1xe2x88x92F2). The phase locking circuitry includes a power splitter 406 for distributing the signal from oscillator 400 to the first input of mixers 408 and 410. A power splitter 412 distributes the signal from VCO 402 to the second input of mixer 410 and to the second input of mixer 408 with a phase shift xcfx861 in phase shifter 414 to generate first I and Q signals from the mixers 408 and 410. Higher frequency components of the first I and Q signals are filtered out and the signals are applied to first inputs of multipliers 422 and 424.
The oscillator 404 operates at the desired offset frequency (F2xe2x88x92F1) or (F1xe2x88x92F2). The output of the oscillator 404 is provided directly to multiplier 422 to provide a second I signal multiplied by the first Q signal. The output of oscillator 404 is further provided to multiplier 424 through a phase shifter 426 to multiply a second Q signal by the first I signal. The phase shifter 426 provides a phase shift xcfx861 matching the phase shift of phase detector 414 for F2xe2x88x92F1, or provides a phase shift xcfx861 matching the phase shift of phase detector 414 with an additional 180xc2x0 for F1xe2x88x92F2. The output of multiplier 422 is subtracted from the output of multiplier 424 in summer 428. The output of summer then provides a voltage control signal to VCO 402 with no |F1+F2| component.
As configured, the phase locking circuitry creates a phase detector, so that the output of the summer 428 provides a DC signal sin(xcfx862), where xcfx862 is a phase difference between the signal F2xe2x88x92F1 or F1xe2x88x92F2 combined from oscillator 400 and VCO 402 and the signal F2xe2x88x92F1 or F1xe2x88x92F2 from the reference oscillator 404. Any 2(F2xe2x88x92F1) or 2(F1xe2x88x92F2) component is canceled. The circuitry enables stable tracking of a minimal frequency offset such as from 0 Hz to 50 KHz with the oscillators providing F1 and F2 operating in the range of 10 GHz with loop bandwidth independent of Fs. The phase locking circuitry is useful in applications like providing a variable Doppler shift for a radar signal.